Publications
TR-2000-1
Poul F. Williams, Henrik R. Andersen, Henrik Hulgaard.
"Satisfiability Checking Using Boolean Expression Diagrams"
In IT University Technical Report Series, October 2000.

TR-2000-2
Poul F. Williams, Antoine Rauzy.
"Greedy Model Checking"
In IT University Technical Report Series, October 2000.

TECHCON '00
Poul F. Williams, Armin Biere, Edmund M. Clarke, Anubhav Gupta.
"Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking"
In Proc. SRC's Sixth Premier Technical Conference (TECHCON '00), Phoenix, Arizona, September 2000.

Ph.D. Thesis
Poul F. Williams
"Formal Verification Based on Boolean Expression Diagrams"
Ph.D. dissertation at Department of Information Technology, Technical University of Denmark, Lyngby, Denmark, August 2000.

IPL '00
Poul F. Williams, Macha Nikolskaia, Antoine Rauzy.
"Bypassing BDD Construction for Reliability Analysis"
In Information Processing Letters (IPL), volume 75, issue 1-2, July 2000. 2000 Elsevier.

CAV '00
Poul F. Williams, Armin Biere, Edmund M. Clarke, Anubhav Gupta.
"Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking"
In Proc. Computer Aided Verification (CAV '00), Lecture Notes in Computer Science, volume 1855, July 2000. 2000 Springer-Verlag.

ICECS '99
Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen.
"Equivalence Checking of Hierarchical Combinational Circuits"
In Proc. 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS '99), September 1999. 1999 IEEE.

TCAD '99
Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen.
"Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams"
In IEEE Transactions on CAD, July 1999. 1999 IEEE.

Berlingske Tidende
Jakob Lichtenberg, Jørn Lind-Nielsen, Poul Frederick Williams.
"Når Computeren Kokser"
In Berlingske Tidende, section Univers, page 6 and 7, April 20, 1999. In Danish.

Reed-Muller '97
Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen.
"Combinational Logic-Level Verification using Boolean Expression Diagrams"
In Proc. 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, September 1997.

Poul Frederick Williams
E-mail: pfw@it-c.dk
Homepage: www.it-c.dk/people/pfw
Live as if your were to die tomorrow.
Learn as if you were to live forever.
(Gandhi)