/////////////////////////////////////////////////
// pc.cpp  // code for ILOG Solver 6.0
// Sathi
// IT-University of Copenhagen  07-April-2004
/////////////////////////////////////////////////

#include <ilsolver/ilosolverany.h>
#include <stdlib.h>
#include <fstream.h>
#include <time.h>
clock_t worst;

ILOSTLBEGIN


struct assignment_pair{
	int varid;
	int value;
};

int main(){
  IloEnv env;
  try {
    IloModel model(env);

	IloIntVar maxslots(env, 8, 8);
    IloIntVar maxramblocks(env, 4, 4);



/*
    char cpuslot[][25] ={
	0	"Slot1"
	1	,"Socket7"
	2	,"SuperSocket7"
	3	,"SlotA"};
	IloAnyArray CpuSlot(env,4,cpuslot[0],,cpuslot[1],cpuslot[2],cpuslot[3]);

    char slot[][25] = {
	// 0    NONE
	   1   "PCI"
	   2  ,"ISA"
	   3  ,"AGP"};
    IloAnyArray Slot(env,3,slot[0],slot[1],slot[2]);


	char ramslot[][25] ={
	0	 "Std72Pin
	1    ,"EDO72Pin"
	2	,"SDRAM168Pin"};

    IloAnyArray RamSlot    	(env,3,ramslot[0],ramslot[1],ramslot[2]);


  char hdbus[][25] ={
	0  "IDE"
	1, "SCSI_UW2"
	2, "SSCI_2" };
  IloAnyArray HdBus(env,3,hdbus[0],hdbus[1],hdbus[2])

 char hdcapacity[][25] ={
	0     "0Gb"
	1	, "9Gb"
	2	, "10Gb"
	3	, "27Gb"
	4	, "31Gb"
	5	, "34Gb"
	6    , "36Gb"
	};

 IloAnyArray HdCapacity(env,7,hdcapacity[0],hdcapacity[1],hdcapacity[2],hdcapacity[3],hdcapacity[4],hdcapacity[5],hdcapacity[6]);


char cpufreq[][25] = {
	0 "75MHz"
	1, "233MHz"
	2, "266MHz"
	3, "333MHz"
	4, "350MHz"
	5, "366MHz"
	6, "400MHz"
	7, "450MHz"
	8, "500MHz"
	9, "600MHz"
	10, "700MHz"
	11, "800MHz"
};

  IloAnyArray CpuFreq(env,12,cpufreq[0],cpufreq[1],cpufreq[2],cpufreq[3],cpufreq[4],cpufreq[5],cpufreq[6],cpufreq[7],cpufreq[8],cpufreq[9],cpufreq[10],cpufreq[11]);


  car ramcapacity[][25]={
	0  "0Mb"
	1, "32Mb"
	2, "64Mb"
	3, "92Mb"
	4, "128Mb"
	5, "160Mb"
	6, "192Mb"
	7, "224Mb"
	8, "256Mb"
	9, "288Mb"
	10, "320Mb"
	11, "352Mb"
	12, "384Mb"
	13, "416Mb"
	14, "448Mb"
	15, "480Mb"
	16, "512Mb"
	17, "544Mb"
	18, "576Mb"
	19, "608Mb"
	20, "640Mb"
	21, "672Mb"
	22, "704Mb"
	23, "736Mb"
	24, "768Mb"
	25, "800Mb"
	26, "832Mb"
	27, "864Mb"
	28, "896Mb"
	29, "928Mb"
	30, "960Mb"
	31, "992Mb"
	32, "1024Mb"
	};

  IloAnyArray RamCapacity{env,33,ramcapacity[0],ramcapacity[1],ramcapacity[2],ramcapacity[3],ramcapacity[4],ramcapacity[5],ramcapacity[6],ramcapacity[7],ramcapacity[8],ramcapacity[9],ramcapacity[10],ramcapacity[11],ramcapacity[12],ramcapacity[13],ramcapacity[14],ramcapacity[15],ramcapacity[16],ramcapacity[17],ramcapacity[18],ramcapacity[19],ramcapacity[20],ramcapacity[21],ramcapacity[22],ramcapacity[23],ramcapacity[24],ramcapacity[25],ramcapacity[26],ramcapacity[27],ramcapacity[28],ramcapacity[29],ramcapacity[30],ramcapacity[31],ramcapacity[32]};


  char motherboardid[][25] ={
	0     "Aopen AK-72 133 ATX"
	1	, "Asus K7M ATX"
	2	, "Microstar 6167 ATX"
	3	, "Acorp 6BX81 ATX"
	4	, "Aopen AX6BP ATX"
	5	, "Abit BH6 ATX"
	6	, "Abit BX6 ATX"
	7	, "Asus P5A-B"
	8	, "Acorp 5ALI 61"
	9	, "Aopen MX6E ATX"
	10  , "Aopen AX59PRO 512KB"
	};

  IloAnyArray MotherboardId(env,11,motherboardid[0],motherboardid[1],motherboardid[2],motherboardid[3],motherboardid[4],motherboardid[5],motherboardid[6],motherboardid[7],motherboardid[8],motherboardid[9],motherboardid[10])

  char processorid[][25] = {
	0  "AMD Athlon 800MHz"
	1, "AMD Athlon 500MHz"
	2, "Intel Pentium III 600MHz"
	3, "Intel Celeron A 366MHz"
	4, "Intel Pentium II 350MHz"
	5, "Intel Pentium II 333MHz"
	6, "AMD K6-2 266MHz 3DNOW"
	7, "Intel Pentium 233MHz MMX"};

  IloAnyArray ProcessorId(env,8,processorid[0],processorid[1],processorid[2],processorid[3],processorid[4],processorid[5],processorid[6],processorid[7]) :


   char harddiskid[][25]={
    0   "No hard disk"
	1, "Quantum Atlas IV 36,4GB"
	2, "IBM DeskStar 34GXP 34,2GB"
	3, "Maxtor DiamondMax 40+ 30,7GB"
	4, "Western Digital Caviar Expert 27,3GB"
	5, "IBM DeskStar 25GP 10,1GB"
	6, "Seagate Barracuda 9 9,1GB"};

	IloAnyArray HarddiskId(env,7,harddiskid[0],harddiskid[1],harddiskid[2],harddiskid[3],harddiskid[4],harddiskid[5],harddiskid[6]);

  char ramid[][25]={
    0  "No RAM block"
	1, "SDRAM PC100 NONAME 256MB"
	2, "SDRAM PC100 NONAME 128MB"
	3, "SDRAM PC133 64MB"
	4, "SDRAM PC100 MCT 64MB"
	5, "SDRAM PC66 32MB"
	6, "Standard RAM u/Paritet 32MB"};

	IloAnyArray RamId(env,7,ramid[0],ramid[1],ramid[2],ramid[3],ramid[4],ramid[5],ramid[6]) ;

  char graphicscardid[][7]={
    0  "Asus AGP-V3400TNT m/TV-In/TV-Out"
  	1, "Diamond Viper 770"
  	2, "Creative Labs Graphics Blaster Riva TNT"
  	3, "ATI Rage Fury m/TV-Out"
  	4, "Matrox Millennium G200"
  	5, "Diamond Monster Fusion"
	6, "ATI All-In-Wonder 128 Bulk"};

  IloAnyArray GraphicsCardId(env,7,graphicscardid[0],graphicscardid[1],graphicscardid[2],graphicscardid[3],graphicscardid[4],graphicscardid[5],graphicscardid[6])

*/
/* MOTHERBOARD
	  public  id			: MotherboardId;
	  private cpuslot		: CpuSlot;
	  private slot			: array MaxSlots of optional Slot;
	  private controllertype	: HdBus;
	  private controllercount	: [0..4];
	  private mincpufreq		: CpuFreq;
	  private maxcpufreq		: CpuFreq;
	  private ramslot		: RamSlot;
	  private ramcapacity		: [0..MaxRamBlocks];
*/

/*
     IloAnyVar mb_id(env,MotherboardId), mb_cpuslot(env,CpuSlot),mb_controllertype(env,HdBus);
     IloIntVar mb_controllercount(env,0,4);
     IloAnyVar mb_mincpufreq(env,CpuFreq);
	 IloAnyVar mb_maxcpufreq(env,CpuFreq);
	 IloAnyVar mb_ramslot(env,Ramslot);
	 IloIntVar mb_ramcapacity(env,0,8);
	 IloIntVarArray mb_SOME_slot(env,8,0,1);
	 IloAnyVar      mb_slot(env,Slot);
	 IloAnyVarArray mb_slot(env,1,mb_slot);
	                mb_slot.add(7,mb_slot);


*/

     IloIntVar mb_id(env,0,10), mb_cpuslot(env,0,3),mb_controllertype(env,0,2);
	 IloIntVarArray mb_SOME_slot(env,8,0,3);
	 IloIntVar mb_controllercount(env,0,4);
     IloIntVar mb_mincpufreq(env,0,11);
	 IloIntVar mb_maxcpufreq(env,0,11);
	 IloIntVar mb_ramslot(env,0,2);
	 IloIntVar mb_ramcapacity(env,0,7);




     model.add(((mb_id==6)&&(mb_cpuslot==0)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==7)&&(mb_ramslot==2)&&(mb_ramcapacity==4)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==2)&&(mb_SOME_slot[7]==3))
              ||((mb_id==5)&&(mb_cpuslot==0)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==7)&&(mb_ramslot==2)&&(mb_ramcapacity==4)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==1)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==2)&&(mb_SOME_slot[7]==3))
              ||((mb_id==8)&&(mb_cpuslot==1)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==0)&&(mb_maxcpufreq==4)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==2)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==8)&&(mb_cpuslot==1)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==0)&&(mb_maxcpufreq==4)&&(mb_ramslot==0)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==2)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==10)&&(mb_cpuslot==1)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==0)&&(mb_maxcpufreq==3)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==10)&&(mb_cpuslot==1)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==0)&&(mb_maxcpufreq==3)&&(mb_ramslot==0)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==3)&&(mb_cpuslot==0)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==9)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==2)&&(mb_SOME_slot[7]==3))
              ||((mb_id==9)&&(mb_cpuslot==0)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==4)&&(mb_ramslot==2)&&(mb_ramcapacity==4)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==2)&&(mb_SOME_slot[3]==2)
                 &&(mb_SOME_slot[4]==3)&&(mb_SOME_slot[5]==0)&&(mb_SOME_slot[6]==0)&&(mb_SOME_slot[7]==0))
              ||((mb_id==4)&&(mb_cpuslot==0)&&(mb_controllertype==1)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==7)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==2)&&(mb_SOME_slot[7]==3))
              ||((mb_id==7)&&(mb_cpuslot==1)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==1)&&(mb_maxcpufreq==6)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==2)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==3)&&(mb_SOME_slot[6]==0)&&(mb_SOME_slot[7]==0))
              ||((mb_id==1)&&(mb_cpuslot==3)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==8)&&(mb_maxcpufreq==10)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==1)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==2)&&(mb_cpuslot==3)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==8)&&(mb_maxcpufreq==10)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==1)&&(mb_SOME_slot[5]==2)&&(mb_SOME_slot[6]==3)&&(mb_SOME_slot[7]==0))
              ||((mb_id==0)&&(mb_cpuslot==3)&&(mb_controllertype==0)&&(mb_controllercount==4)
                 &&(mb_mincpufreq==8)&&(mb_maxcpufreq==11)&&(mb_ramslot==2)&&(mb_ramcapacity==3)
                 &&(mb_SOME_slot[0]==1)&&(mb_SOME_slot[1]==1)&&(mb_SOME_slot[2]==1)&&(mb_SOME_slot[3]==1)
                 &&(mb_SOME_slot[4]==2)&&(mb_SOME_slot[5]==3)&&(mb_SOME_slot[6]==0)&&(mb_SOME_slot[7]==0))
              );


   IloIntVar  pro_id(env,0,7);
   IloIntVar  pro_cpuslot(env,0,3);
   IloIntVar  pro_freq(env,0,11);

  model.add(((pro_id==6)&&(pro_cpuslot==1)&&(pro_freq==2))
	      ||((pro_id==0)&&(pro_cpuslot==3)&&(pro_freq==11))
		  ||((pro_id==1)&&(pro_cpuslot==3)&&(pro_freq==8))
	      ||((pro_id==7)&&(pro_cpuslot==1)&&(pro_freq==1))
		  ||((pro_id==3)&&(pro_cpuslot==0)&&(pro_freq==5))
	      ||((pro_id==4)&&(pro_cpuslot==0)&&(pro_freq==4))
		  ||((pro_id==2)&&(pro_cpuslot==0)&&(pro_freq==9))
	      ||((pro_id==5)&&(pro_cpuslot==0)&&(pro_freq==3))
	  );

  IloIntVar  hd1_id(env,0,6);
  IloIntVar  hd1_bus(env,0,2);
  IloIntVar  hd1_capacity(env,0,6);

  model.add(  ((hd1_id==0)&&(hd1_bus==0)&&(hd1_capacity==0))
  			||((hd1_id==0)&&(hd1_bus==1)&&(hd1_capacity==0))
  			||((hd1_id==5)&&(hd1_bus==0)&&(hd1_capacity==2))
  			||((hd1_id==2)&&(hd1_bus==0)&&(hd1_capacity==5))
  			||((hd1_id==3)&&(hd1_bus==0)&&(hd1_capacity==4))
  			||((hd1_id==1)&&(hd1_bus==1)&&(hd1_capacity==6))
  			||((hd1_id==6)&&(hd1_bus==1)&&(hd1_capacity==1))
  			||((hd1_id==4)&&(hd1_bus==0)&&(hd1_capacity==3))
	 );


	   IloIntVar  hd2_id(env,0,6);
	   IloIntVar  hd2_bus(env,0,2);
	   IloIntVar  hd2_capacity(env,0,6);

	   model.add(  ((hd2_id==0)&&(hd2_bus==0)&&(hd2_capacity==0))
	   			||((hd2_id==0)&&(hd2_bus==1)&&(hd2_capacity==0))
	   			||((hd2_id==5)&&(hd2_bus==0)&&(hd2_capacity==2))
	   			||((hd2_id==2)&&(hd2_bus==0)&&(hd2_capacity==5))
	   			||((hd2_id==3)&&(hd2_bus==0)&&(hd2_capacity==4))
	   			||((hd2_id==1)&&(hd2_bus==1)&&(hd2_capacity==6))
	   			||((hd2_id==6)&&(hd2_bus==1)&&(hd2_capacity==1))
	   			||((hd2_id==4)&&(hd2_bus==0)&&(hd2_capacity==3))
	 	 );


    IloIntVar ram1_id(env,0,6);
    IloIntVar ram1_slot(env,0,2);
    IloIntVar ram1_capacity(env,0,32);

    model.add(
			  ((ram1_id==0)&&(ram1_slot==0)&&(ram1_capacity==0))
			||((ram1_id==0)&&(ram1_slot==2)&&(ram1_capacity==0))
			||((ram1_id==6)&&(ram1_slot==0)&&(ram1_capacity==1))
			||((ram1_id==2)&&(ram1_slot==2)&&(ram1_capacity==4))
			||((ram1_id==5)&&(ram1_slot==2)&&(ram1_capacity==1))
			||((ram1_id==4)&&(ram1_slot==2)&&(ram1_capacity==2))
			||((ram1_id==3)&&(ram1_slot==2)&&(ram1_capacity==2))
			||((ram1_id==1)&&(ram1_slot==2)&&(ram1_capacity==8))
	);


    IloIntVar ram2_id(env,0,6);
    IloIntVar ram2_slot(env,0,2);
    IloIntVar ram2_capacity(env,0,32);

    model.add(
			  ((ram2_id==0)&&(ram2_slot==0)&&(ram2_capacity==0))
			||((ram2_id==0)&&(ram2_slot==2)&&(ram2_capacity==0))
			||((ram2_id==6)&&(ram2_slot==0)&&(ram2_capacity==1))
			||((ram2_id==2)&&(ram2_slot==2)&&(ram2_capacity==4))
			||((ram2_id==5)&&(ram2_slot==2)&&(ram2_capacity==1))
			||((ram2_id==4)&&(ram2_slot==2)&&(ram2_capacity==2))
			||((ram2_id==3)&&(ram2_slot==2)&&(ram2_capacity==2))
			||((ram2_id==1)&&(ram2_slot==2)&&(ram2_capacity==8))
	);


    IloIntVar ram3_id(env,0,6);
    IloIntVar ram3_slot(env,0,2);
    IloIntVar ram3_capacity(env,0,32);

    model.add(
			  ((ram3_id==0)&&(ram3_slot==0)&&(ram3_capacity==0))
			||((ram3_id==0)&&(ram3_slot==2)&&(ram3_capacity==0))
			||((ram3_id==6)&&(ram3_slot==0)&&(ram3_capacity==1))
			||((ram3_id==2)&&(ram3_slot==2)&&(ram3_capacity==4))
			||((ram3_id==5)&&(ram3_slot==2)&&(ram3_capacity==1))
			||((ram3_id==4)&&(ram3_slot==2)&&(ram3_capacity==2))
			||((ram3_id==3)&&(ram3_slot==2)&&(ram3_capacity==2))
			||((ram3_id==1)&&(ram3_slot==2)&&(ram3_capacity==8))
	);


    IloIntVar ram4_id(env,0,6);
    IloIntVar ram4_slot(env,0,2);
    IloIntVar ram4_capacity(env,0,32);

    model.add(
			  ((ram4_id==0)&&(ram4_slot==0)&&(ram4_capacity==0))
			||((ram4_id==0)&&(ram4_slot==2)&&(ram4_capacity==0))
			||((ram4_id==6)&&(ram4_slot==0)&&(ram4_capacity==1))
			||((ram4_id==2)&&(ram4_slot==2)&&(ram4_capacity==4))
			||((ram4_id==5)&&(ram4_slot==2)&&(ram4_capacity==1))
			||((ram4_id==4)&&(ram4_slot==2)&&(ram4_capacity==2))
			||((ram4_id==3)&&(ram4_slot==2)&&(ram4_capacity==2))
			||((ram4_id==1)&&(ram4_slot==2)&&(ram4_capacity==8))
	);

   IloIntVar graphics_id(env,0,6);
   IloIntVar  graphics_slot(env,1,3);

  model.add(
	   		 ((graphics_id==0)&&(graphics_slot==3))
	    ||
	   		 ((graphics_id==3)&&(graphics_slot==3))
	    ||
	   		 ((graphics_id==6)&&(graphics_slot==1))
	    ||
	   		 ((graphics_id==2)&&(graphics_slot==3))
	    ||
	   		 ((graphics_id==5)&&(graphics_slot==1))
	    ||
	   		 ((graphics_id==4)&&(graphics_slot==3))
	    ||
	   		 ((graphics_id==1)&&(graphics_slot==3))

	 );

  IloIntVar pc_clock(env,0,11);
  IloIntVar pc_memory(env,0,32);





    //IloIntVarArray   vars(env,13,0,40);
    IloExtractableArray iloextractablearray(env,13);


    vector<int> varDom;
    vector<IloIntVar*> varPtr;

    varPtr.push_back(&mb_id);
	varDom.push_back(11);
    varPtr.push_back(&pro_id);
	varDom.push_back(8);
    varPtr.push_back(&hd1_id);
	varDom.push_back(7);
    varPtr.push_back(&hd1_capacity);
	varDom.push_back(7);
    varPtr.push_back(&hd2_id);
	varDom.push_back(7);
    varPtr.push_back(&hd2_capacity);
	varDom.push_back(7);
    varPtr.push_back(&ram1_id);
	varDom.push_back(7);
    varPtr.push_back(&ram2_id);
	varDom.push_back(7);
    varPtr.push_back(&ram3_id);
	varDom.push_back(7);
    varPtr.push_back(&ram4_id);
	varDom.push_back(7);
    varPtr.push_back(&graphics_id);
	varDom.push_back(7);
    varPtr.push_back(&pc_clock);
	varDom.push_back(12);
    varPtr.push_back(&pc_memory);
	varDom.push_back(33);


/*
    model.add(mb_id==vars[0]);
    model.add(pro_id==vars[1]);
    model.add(hd1_id==vars[2]);
    model.add(hd1_capacity==vars[3]);
    model.add(hd2_id==vars[4]);
    model.add(hd2_capacity==vars[5]);
    model.add(ram1_id==vars[6]);
    model.add(ram2_id==vars[7]);
    model.add(ram3_id==vars[8]);
    model.add(ram4_id==vars[9]);
    model.add(graphics_id==vars[10]);
    model.add(pc_clock==vars[11]);
    model.add(pc_memory==vars[12]);
*/


    int var_size[13];

    var_size[0]=11;
    var_size[1]=8;
    var_size[2]=7;
    var_size[3]=7;
    var_size[4]=7;
    var_size[5]=7;
    var_size[6]=7;
    var_size[7]=7;
    var_size[8]=7;
    var_size[9]=7;
    var_size[10]=7;
    var_size[11]=12;
    var_size[12]=33;

    int num_var=13;

    int *var_isvalid[13];
    int is_assigned[13];
    for(int i=0;i<num_var;i++){
		var_isvalid[i]= new int[var_size[i]];
		is_assigned[i]=0;
		for(int j=0; j<var_size[i];j++){
			var_isvalid[i][j]=1;
		}
	}


  int**  var_shownValidThisStep = new int*[varPtr.size()];
  for(int i=0;i< varPtr.size();i++)
    {
      var_shownValidThisStep[i] = new int[varDom[i]];
      for(int j=0; j < varDom[i]; j++)
        var_shownValidThisStep[i][j] = 0;
    }


	assignment_pair  assignments[13];
	assignment_pair  old_assignments[13];
	int old_num_assigns=0;
	int start_from_scratch=1;

/**General PC Rules **/

   model.add((mb_cpuslot==pro_cpuslot)&&(pro_freq>=mb_mincpufreq)&&(pro_freq<=mb_maxcpufreq));
   model.add(mb_controllertype==hd1_bus);
   model.add(mb_controllertype==hd2_bus);

   model.add(mb_ramslot==ram1_slot);
   model.add(mb_ramslot==ram2_slot);
   model.add(mb_ramslot==ram3_slot);
   model.add(mb_ramslot==ram4_slot);

  IloIntVar ram1_present(env,0,1);
  IloIntVar ram2_present(env,0,1);
  IloIntVar ram3_present(env,0,1);
  IloIntVar ram4_present(env,0,1);

   model.add((ram1_present==0)||(ram1_id>0));
   model.add((ram1_present==1)||(ram1_id<1));

   model.add((ram2_present==0)||(ram2_id>0));
   model.add((ram2_present==1)||(ram2_id<1));

   model.add((ram3_present==0)||(ram3_id>0));
   model.add((ram3_present==1)||(ram3_id<1));

   model.add((ram4_present==0)||(ram4_id>0));
   model.add((ram4_present==1)||(ram4_id<1));

   model.add(mb_ramcapacity>=(ram1_present+ram2_present+ram3_present+ram4_present));


   model.add((!(ram2_id>0)||(ram1_id>0)));
   model.add((!(ram3_id>0)||(ram1_id>0)));
   model.add((!(ram3_id>0)||(ram2_id>0)));
   model.add((!(ram4_id>0)||(ram1_id>0)));
   model.add((!(ram4_id>0)||(ram2_id>0)));
   model.add((!(ram4_id>0)||(ram3_id>0)));


   model.add(
	   	  (mb_SOME_slot[0]==graphics_slot)
	   	||(mb_SOME_slot[1]==graphics_slot)
	   	||(mb_SOME_slot[2]==graphics_slot)
	   	||(mb_SOME_slot[3]==graphics_slot)
	   	||(mb_SOME_slot[4]==graphics_slot)
	   	||(mb_SOME_slot[5]==graphics_slot)
	   	||(mb_SOME_slot[6]==graphics_slot)
	   	||(mb_SOME_slot[7]==graphics_slot)
	   	);


   model.add(hd1_id>0);
   model.add(ram1_id>0);
   model.add(pc_clock==pro_freq);
   model.add(pc_memory==(ram1_capacity+ram2_capacity+ram3_capacity+ram4_capacity));


    IloSolver solver(model);
    /*
    IloInt solutionCounter = 0;
    solver.startNewSearch();
    while(solver.next()){
	++solutionCounter;
	if(solutionCounter==1) cerr<<"Found One Solution"<<endl;
    }

   solver.endSearch();
   solver.out()<<" SOlutions "<<solutionCounter<<endl;
    */
    ifstream ti("pc.ti");
    int num_assigns=0;
    int varid;
    int value;
    int inp;
    int inp2;
    int itr_count=0;
    ti>>inp;ti>>inp2;
    int start_assign=0;

    do{

		clock_t t1=clock();


		for(int k=0;k<old_num_assigns;k++)
			old_assignments[k]=assignments[k];
		ti>>inp;ti>>inp2;
		while(inp!=-1 && inp != -2){
			varid=inp;
			value=inp2;
			assignments[num_assigns].varid=varid;
			assignments[num_assigns].value=value;
			//cerr<<"varid "<<varid<<"    "<<"value "<<value<<endl;
			num_assigns++;
			ti>>inp;ti>>inp2;
		}

		//make the assignments
		//check for each valid value in previous request.
		//thats all
		if(num_assigns==old_num_assigns+1){
			int i;
			for(i=0;i<old_num_assigns;i++){
				if(assignments[i].varid!=old_assignments[i].varid || assignments[i].value!=old_assignments[i].value)
					break;
			}
			if(i==old_num_assigns)
				start_from_scratch=0;
			else
				start_from_scratch=1;

		}
		else
			start_from_scratch=1;

		if(start_from_scratch){
			//remove old_num_assigns of iloextractable array constraints from the model
			//valid all values are valid values
			for(int i=0;i<old_num_assigns;i++){
				model.remove(iloextractablearray[i]);
			}
			for(int i=0; i<num_var ; i++)
				for(int j=0; j<var_size[i];j++)
					var_isvalid[i][j]=1;
			for(int i=0; i<num_var ; i++)
				is_assigned[i]=0;

			start_assign=0;
		}
		else
		  start_assign=old_num_assigns;

		for(int i=start_assign;i<num_assigns;i++){
			iloextractablearray[i]=model.add(*varPtr[assignments[i].varid]==assignments[i].value);
			is_assigned[assignments[i].varid]=1;
		}


       	for(int i = 0; i < varPtr.size(); i++)
       		for(int j = 0; j < varDom[i];j++)
       			var_shownValidThisStep[i][j] = 0;

		for(int i=0; i<num_var ; i++){

			if(is_assigned[i])  continue;

			for(int j=0; j<var_size[i];j++){

				if(!var_isvalid[i][j]) continue;
	 			if (var_shownValidThisStep[i][j]) continue;

				IloExtractable current=model.add(*varPtr[i]==j);







				solver.startNewSearch();

				if(solver.next()){
      			           for (int g = 0; g < varPtr.size(); g++) {
				     var_shownValidThisStep[g][int(solver.getValue(*varPtr[g]))] = 1;
				   }
 				}
				else
					var_isvalid[i][j]=0;

				solver.endSearch();

				model.remove(current);
			}

		}

		itr_count++;
		if(itr_count%100)
			cerr<<itr_count<<" ";
		old_num_assigns=num_assigns;
		num_assigns=0;
		//ti>>inp;ti>>inp2;

				clock_t t2=clock();

				if(itr_count==0)  worst = (t2-t1);

				if(worst < (t2-t1)) worst = (t2-t1);




	}while(inp!=-2);

    solver.out()<<"End Simulation of "<<itr_count<<" Requests"<<endl;
	solver.out()<<"Worst Time is "<<(worst/(double)CLOCKS_PER_SEC) << endl;

	}
  catch (IloException& ex) {
    cerr << "Error: " << ex << endl;
  }
  env.end();
  return 0;
}